5M570ZF256C5N IC CPLD 440MC 9NS 256FBGA 9 ns 1.71V ~ 1.89V I/O 159

Funcations of 5M570ZF256C5N

MAX V devices contain a two-dimensional row- and column-based architecture to
implement custom logic. Row and column interconnects provide signal interconnects
between the logic array blocks (LABs).

Each LAB in the logic array contains 10 logic elements (LEs). An LE is a small unit of
logic that provides fcient implementation of user logic functions. LABs are grouped
into rows and columns across the device. The MultiTrack interconnect provides fast
granular timing delays between LABs. The fast routing between LEs provides
minimum timing delay for added levels of logic versus globally routed interconnect
structures.

The I/O elements (IOEs) located after the LAB rows and columns around the
periphery of the MAX V device feeds the I/O pins. Each IOE contains a bidirectional
I/O buffer with several advanced features. I/O pins support Schmitt trigger inputs .
and various single-ended standards, such as 33-MHz, 32-bit PCITM, and LVTTL.

Environmental & Export Classifications of 5M570ZF256C5N